1. Field of the Invention
The present invention relates to the field of timer circuits. More particularly, the present invention relates to a method and architecture for a timer circuit having a delay that is inversely proportional to temperature.
2. Related Art
There are a number of timer circuits known in the art that are applied in circuits that require an intentional delay for timing coordination. Most of these applications have a timing delay that changes proportional to changes in temperature. One common application of such a timer is in a basic ring oscillator circuit. Many applications, however, require a circuit having a delay that does not vary appreciatively with process, voltage or temperature. Examples of such applications are command timers, command cycle timers and deep sleep mode timers.
Conventional Art FIG. 1 illustrates an example of such a conventional timer circuit 100, a VNBIAS Timer. This is a deep sleep mode timer that includes metal trim options. These types of timers receive a reference level, such as VNBIAS, that may be generated from a bandgap reference circuit on a chip. In this approach, the current through the leg in the bandgap reference circuit (not shown) sets the VNBIAS reference voltage 105 and this current may be mirrored into the pull-down path 120 of the timer 100. The corresponding NMOS 122 (with VNBIAS at the gate) is typically sized to control the current through leg 120. To create a faster or slower delay in the timer 100, NMOS type gate-capacitors 130a, 130b and 130c can be selectively added or removed as metal trim options to enable more or less capacitance on the output node of the current starved inverter, thereby increasing or decreasing the delay time of circuit 100. During operation, this approach produces a constant delay based on the capacitor loads and requires designing for a worst-case delay with no real-time adjustment for temperature variations or other environmental effects that may impact the delay time of the chip.
Certain timers, such as write back timers, wordline timers, sense amp set to CSL timers and refresh oscillators have further complications that render the conventional timers inadequate. For example, because the strap resistance between the deep trench capacitor and the pass gate in a 1T memory cell is more resistive at lower temperatures and less resistive at higher temperatures, write back into the cell needs to be longer at low temperatures and shorter at high temperatures. Also due to the strap resistance, in order to get enough signal margin so that sense amps can read the value in the cell, the wordline to set time needs to be on longer for lower temperatures and shorter for higher temperatures. Because the threshold voltages (VTs) of the pass gates to the sense amps and the cross-coupled nfet and pfet pairs of the sense amp get higher with lower temperature, the sense amp takes longer to set. Therefore the sense amp set to CSL time needs to be longer for lower temperatures than for higher temperatures. Also, the retention time of the 1T memory cell is shorter at higher temperatures and longer at lower temperatures. Therefore, the memory cells need to be refreshed more frequently at higher temperatures and less frequently at lower temperatures.